Principal Investigators: Vivienne Sze, Joel Emer

 

The architectural configuration of an ANN and its performance and energy efficiency hinge on many design decisions that ultimately emerge from the characteristics of the underlying synapse technology. Today, there is no way to rapidly and systematically explore the large design space of possible ANN accelerator architectures that a given device technology can support. This project pursues an integrated framework that includes energy-modeling and performance evaluation tools to systematically explore and estimate the energy-efficiency and performance of ANN architectures with full consideration of the electrical characteristics of the synaptic elements and interface circuits. This framework will be used to systematically guide the exploration of ANN accelerator design space all the way from the device backbone to the architectural level.